As semiconductor systems are developed to operate at a high speed, high data transmission rates (or data communication at high bandwidth) between semiconductor chips constituting each semiconductor system have been increasingly in demand. In response to such a demand, various pre-fetch schemes have been proposed. The pre-fetch scheme may correspond to a design technique that latches data inputted in series and outputs the latched data in parallel. To obtain the parallel data, clock signals having different phases, for example, multi-phase clock signals are generated in the semiconductor chips and the multi-phase clock signals are used to input or output the data.